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Designing Vlsi Network Nodes to Reduce Memory Traffic in a Shared Memory Parallel Computer (Classic Reprint)/en-ca/designing-vlsi-network-nodes-to-reduce-memory-traffic-in-a-shared-memory-parallel-computer-classic-reprint/3F53651A-0FCB-4CBA-96A1-46376621235C.html3F53651A-0FCB-4CBA-96A1-46376621235C
Designing VLSI Network Nodes to Reduce Memory Traffic in a Shared Memory Parallel Computer